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?1 e00766a19 sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 1.1cm (0.44 type) ntsc/pal color lcd panel description the LCX032ANB is a 1.1cm diagonal active matrix tft-lcd panel addressed by polycrystalline silicon super thin film transistors with built-in peripheral driving circuit. this panel provides full-color representation in ntsc/pal mode. rgb dots are arranged in a delta pattern featuring high picture quality of no fixed color patterns, which is inherent in vertical stripes and mosaic pattern arrangements. features the number of active dots: 113,578 (0.44 type; 1.1cm in diagonal) horizontal resolution: 260 tv lines high optical transmittance: 4.8% (typ.) high contrast ratio with normally white mode: 200 (typ.) built-in h and v drivers (built-in input level conversion circuit, ttl drive possible) high quality picture representation with rgb delta arranged color filters full-color representation ntsc/pal compatible up/down and/or right/left inverse display function 4:3 and 16:9 aspect switching function power save mode (through current reduction by stop of level shifter and scanner during power supply cutoff) element structure dots total dots : 537 (h) 222 (v) = 119,214 active dots: 521 (h) 218 (v) = 113,578 built-in peripheral driver using polycrystalline silicon super thin film transistors. applications viewfinders super compact liquid crystal monitors etc. LCX032ANB
?2 LCX032ANB block diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 h shift register v level conversion circuit v shift register c s lc com pad v dd v ss vst vck stb en dwn rgt hst hck2 hck1 blk blue red green com h level conversion circuit
3 LCX032ANB absolute maximum ratings (v ss = 0v) h and v driver supply voltages v dd 1.0 to +17 v common pad voltage com 1.0 to +17 v h driver input pin voltage hst, hck1, hck2 1.0 to +17 v rgt v driver input pin voltage vst, vck, dwn, 1.0 to +17 v en, blk power save mode input pin voltage stb 1.0 to +17 v video signal input pin voltage green, red, blue 1.0 to +15 v operating temperature topr 10 to +70 c storage temperature tstg 30 to +85 c operating conditions (v ss = 0v) supply voltage v dd 11.4 to 14.0 v input pulse voltage (vp-p of all input pins except video signal input pins) vin 2.6v (more than) pin description pin no. 1 2 3 4 5 6 7 8 com green red blue blk hck1 hck2 hst common voltage of panel video signal (g) to panel video signal (r) to panel video signal (b) to panel top/bottom block display pulse clock pulse for h shift register drive clock pulse for h shift register drive start pulse for h shift register drive 9 10 11 12 13 14 15 16 rgt dwn en stb vck vst vss v dd drive direction pulse for h shift register (h: normal, l: reverse) drive direction pulse for v shift register (h: normal, l: reverse) enable pulse for gate selection for power save mode control (l-power save mode) clock pulse for v shift register drive start pulse for v shift register drive gnd (h, v drivers) power supply for h and v drivers symbol description pin no. symbol description
4 LCX032ANB input equivalent circuit to prevent static charges, protective diodes are provided for each pin except the power supply. in addition, protective resistors are added to all pins except video signal input. all pins are connected to vss with a high resistance of 1m ? (typ.). the equivalent circuit of each input pin is shown below: (the resistor value: typ.) (1) video signal input input v dd from h driver signal line 1m ? (2) hck1, hck2 v dd 250 ? 250 ? 250 ? 250 ? level conversion circuit (2-phase input) hck1 hck2 1m ? 1m ? (3) hst level conversion circuit (single- phase input) 250 ? 250 ? v dd input 1m ? (4) rgt, vst, en, vck, dwn, stb level conversion circuit (single- phase input) 2.5k ? 2.5k ? v dd input 1m ? (6) com input 1m ? lc v dd level conversion circuit (single- phase input) 2.5k ? 2.5k ? v dd input 1m ? 28k ? (5) blk
5 LCX032ANB level conversion circuit the LCX032ANB has a built-in level conversion circuit in the clock input unit located inside the panel. the circuit voltage is stepped up to v dd inside the panel. this level conversion circuit meets the specifications of a 3.0v power supply of the externally-driven ic. 1. i/o characteristics of level conversion circuit (for a single-phase input unit) an example of the i/o voltage characteristics of a level conversion circuit is shown in the figure to the right. the input voltage value that becomes half the output voltage (after voltage conversion) is defined as vth. the vth value varies depending on the v dd voltage. the vth values under standard conditions are indicated in the table below. (hst, vst, en, dwn, stb, rgt, vck and blk in the case of a single-phase input) v dd = 12.0v v dd 2 v dd vth input voltage [v] example of single-phase i/o characteristics output voltage (inside panel) item vth voltage of circuit vth 0.35 1.50 2.60 v symbol min. typ. max. unit (for a differential input unit) an example of i/o voltage characteristics of a level conversion circuit for a differential input is shown in the figure to the right. although the characteristics, including those of the vth voltage, are basically the same as those for a single-phased input, the two- phased input phase is defined. (refer to clock timing conditions.) v dd 2 v dd vth input voltage [v] example of differential i/o characteristics output voltage (inside panel) 2. current characteristics at the input pin of level conversion circuit a slight pull-in current is generated at the input pin of the level conversion circuit. (the equivalent circuit is shown to the right.) the current volume increases as the voltage at the input pin decreases, and is maximized when the pin is grounded. (refer to electrical characteristics.) v dd output hck1 input hck2 input level conversion equivalent circuit 0 0 max. value input pin voltage [v] 10 pull-in current characteristics at the input pin input pin current
6 LCX032ANB input signals 1. input signal voltage conditions (v ss = 0v, v dd = 11.4 to 14v) item h driver input voltage (hst, hck1, hck2, rgt, stb) (low) (high) (low) (high) vhil vhih vvil vvih v com 0.35 2.6 0.35 2.6 vvc 0.45 0.0 5.0 0.0 5.0 vvc 0.3 0.35 5.5 0.35 5.5 vvc 0.15 v v v v v v driver input voltage (vst, vck1, vck2, dwn, en) common voltage of panel symbol min. typ. max. unit note) video signal shall be symmetrical to video signal center voltage vvc. supplement1) video signal input range is set within the range shown below for v dd and v ss . also, video signal white level is defined for vvc as shown below. item video signal input range video signal input white level vsig vsigl v ss + 1.3 0.5 v dd 1.8 v v symbol min. typ. max. unit aaaaa a aaa a a aaa a a aaa a aaaaa vsigl white level vsigl video signal input range max. v dd 1.8 [v] min. v ss + 1.3 [v] v dd v dd 1.8 vvc v ss + 1.3 v ss supplement2) when power save mode is used, use video signal and com pin within the condition 0.15v to prevent dc applying to lcd.
7 LCX032ANB hst rise time hst fall time hst data set-up time hst data hold time hckn ? 2 rise time hckn ? 2 fall time hck1 fall to hck2 rise time hck1 rise to hck2 fall time vst rise time vst fall time vst data set-up time vst data hold time vck rise time vck fall time en rise time en fall time en fall to vck rise/fall time vck rise/fall to en rise time blk rise time blk fall time blk pulse width blk fall to en rise time trhst tfhst tdhst thhst trhckn tfhckn to1hck to2hck trvst tfvst tdvst thvst trvck tfvck tren tfen tovck tdvck trblk tfblk twblk tdenb 170 455 15 15 50 50 100 100 600 135 135 0 0 32 32 3000 500 1.0 700 30 30 200 50 30 30 15 15 100 100 50 20 100 100 100 100 3500 1000 100 100 800 ns s ns ms ns item symbol min. typ. max. unit hst hck vst vck en blk ? 3 ? 2 hckn means hck1, hck2. (fhckn = 1.84mhz, fvckn = 7.865khz) ? 3 blk pulse is used only for 16:9 mode. for 4:3 mode, connect to v ss . 2. clock timing conditions (ta = 25 c, input voltage = 3.0v, v dd = 12.0v)
8 LCX032ANB hst rise time hst hck hst fall time hst data set-up time hst data hold time hckn ? 2 rise time hckn ? 2 fall time hck1 fall to hck2 rise time hck1 rise to hck2 fall time hckn ? 2 duty cycle 50% to1hck = 0ns to2hck = 0ns hckn ? 2 duty cycle 50% to1hck = 0ns to2hck = 0ns hckn ? 2 duty cycle 50% to1hck = 0ns to2hck = 0ns tdhst = 135ns thhst = 135ns tdhst = 135ns thhst = 135ns trhst tfhst tdhst thhst trhckn tfhckn to1hck to2hck item symbol waveform conditions 90% 10% 10% 90% hst trhst tfhst 50% 50% hst hck1 tdhst thhst 50% 50% ? 4 ? 2 hckn 10% 10% 90% 90% trhckn tfhckn 50% 50% hck1 to2hck to1hck 50% 50% hck2 ? 4
9 LCX032ANB ? 4 definitions: the right-pointing arrow ( ) means +. the left-pointing arrow ( ) means . the black dot at an arrow ( ) indicates the start of measurement. vst rise time vst vck en vst fall time vst data set-up time vst data hold time vck rise time vck fall time en rise time en fall time en fall to vck rise/fall time vck rise/fall to en rise time vck duty cycle 50% vck duty cycle 50% vck duty cycle 50% tdvst = 32s thvst = 32s vck duty cycle 50% vck duty cycle 50% trvst tfvst tdvst thvst trvck tfvck tren tfen tovck tdvck blk blk rise time blk fall time blk pulse width blk fall to en rise time trblk tfblk twblk tdenb item symbol waveform conditions 90% 10% 10% 90% vst trvst tfvst 50% 50% ? 4 vst vck tdvst thvst 50% 50% vck 10% 10% 90% 90% trvck tfvck 90% 90% 10% 10% tfen tren en 50% 50% vck en tovck 50% 50% ? 4 tdvck tovck tdvck 50% 50% 90% 10% 10% 90% trblk tfblk 50% blk en tdenb 50% 50% twblk ? 4
10 LCX032ANB electrical characteristics 1. horizontal drivers (ta = 25 c, v dd = 12.0v, input voltage = 3.0v) item input pin capacitance hckn hst input pin current hck1 hck2 hst rgt stb video signal input pin capacitance chckn chst ihck1 ihck2 ihst irgt istb csig hck1 = gnd hck2 = gnd hst = gnd rgt = gnd stb = gnd 500 500 300 100 100 5 5 250 250 100 25 25 50 10 10 pf pf a a a a a pf symbol min. typ. max. unit condition 2. vertical drivers item input pin capacitance vck vst vst en dwn vck blk cvck cvst ivst ien idwn ivck iblk 100 5 5 25 10 10 pf pf a symbol min. typ. max. unit condition 3. total power consumption of the panel item total power consumption of the panel (ntsc) power consumption during power save pwr 30 0.6 50 mw mw symbol min. typ. max. unit 4. vcom input resistance item vcom vss input resistance video signal vss input resistance rcom rsig 0.5 0.5 1 1 1.2 1.2 m ? m ? symbol min. typ. max. unit vst, en, dwn, vck, blk = gnd
11 LCX032ANB electro-optical characteristics (ta = 25 c, ntsc mode) item contrast ratio v dd = 12.0v vsig = 6.0 4.0v 60 c 25 c 60 c x y x y x y 25 c 60 c 25 c 60 c 25 c 60 c r vs. g b vs. g 0 c 25 c 0 c 25 c 60 c 60 min. cr 4.0 60 cr 4.0 25 t rx ry gx gy bx by v 90-25 v 90-60 v 50-25 v 50-60 v 10-25 v 10-60 v 50rg v 50bg ton0 ton25 toff0 toff25 f yt60 70 70 3.8 0.580 0.300 0.250 0.550 0.105 0.070 1.1 1.0 1.5 1.5 2.2 2.1 200 200 4.8 0.620 0.340 0.290 0.590 0.140 0.110 1.6 1.5 2.0 1.9 2.5 2.4 0.10 0.10 30 20 65 20 0.660 0.380 0.330 0.630 0.175 0.150 2.2 2.1 2.5 2.5 3.2 3.1 0.25 0.45 100 40 150 60 40 20 1 2 3 4 5 6 7 8 % cie standards v v ms db s optical transmittance chromaticity r g b v 90 v 50 v 10 on time off time v-t characteristics half tone color reproduction range response time flicker image retention time symbol measurement method min typ. max. unit
12 LCX032ANB

basic measurement conditions (1) driving voltage v dd = 12.0v vvc = 6.0v, v com = 5.7v (2) measurement temperature 25 c unless otherwise specified. (3) measurement point one point in the center of screen unless otherwise specified. (4) measurement systems two types of measurement system are used as shown below. (5) rgb input signal voltage (vsig) vsig = 6.0 v ac [v] (v ac : signal amplitude) ? measurement system i lcd panel luminance meter measurement equipment back light: color temperature 8500k, +0.004uv (25 c) ? back light spectrum (reference) is listed on another page. optical fiber lcd panel light receptor lens drive circuit light source back light 3.5mm ? measurement system ii measurement equipment light detector 1. contrast ratio contrast ratio (cr 4.0 ) is given by the following formula (1). cr 4.0 = ...(1) l 4.0 (white): surface luminance of the tft-lcd panel at v dd = 12.0v, vvc = 6.0v, v com = 5.7v and the rgb signal amplitude v ac = 0.5v. l 4.0 (black): surface luminance of the panel at v ac = 4.0v. l 4.0 (white) l 4.0 (black)
13 LCX032ANB 2. optical transmittance optical transmittance (t) is given by the following formula (2). t = 100 [%] ...(2) l (white) is the same expression as defined in the "contrast ratio" section. 3. chromaticity chromaticity of the panels are measured by system i . raster modes of each color are defined by the representations at the input signal amplitude conditions shown in the table below. system i uses chromaticity of x and y on the cie standards here. signal amplitudes (v ac ) supplied to each input r input g input b input raster r g b 0.5 4.0 4.0 4.0 0.5 4.0 4.0 4.0 0.5 (unit: v) 4. v-t characteristics v-t characteristics, the relationship between signal amplitude and the transmittance of the panels, are measured by system ii . v 90 , v 50 and v 10 correspond to the each voltage which defines 90%, 50% and 10% of transmittance respectively. (transmittance at v ac = 0.5v is 100%.) 5. half tone color reproduction range half tone color reproduction range of the lcd panels is characterized by the differences between the v-t characteristics of r, g and b. the differences of these v-t characteristics are measured by system ii . system ii defines signal voltages of each r, g, b raster modes which correspond to 50% of transmittance, v 50r , v 50g and v 50b respectively. v 50rg and v 50bg , the voltage differences between v 50r and v 50g , v 50b and v 50g , are simply given by the following formulas (3) and (4) respectively. v 50rg = v 50r v 50g ...(3) v 50bg = v 50b v 50g ...(4) 90 50 10 v 90 v 50 v 10 v ac signal amplitude [v] transmittance [%] 100 50 0 v 50r v 50b v 50g v ac signal amplitude [v] transmittance [%] v 50rg v 50bg g raster b raster r raster l (white) luminance of back light
14 LCX032ANB 6. response time response time ton and toff are defined by the formulas (5) and (6) respectively. ton = t1 ton ...(5) toff = t2 toff ...(6) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. the relationships between t1, t2, ton and toff are shown in the right figure. 7. flicker flicker (f) is given by the formula (7). dc and ac (ntsc: 30hz, rms, pal: 25hz, rms) components of the panel output signal for gray raster ? mode are measured by a dc voltmeter and a spectrum analyzer in system ii . f (db) = 20log {} ...(7) 8. image retention time apply the monoscope signal to the lcd panel for 60 minutes and then change this signal to the gray scale of vsig = 6.0 v ac (v ac : 3 to 4v), judging by sight at v ac that hold the maximum image retention, measure the time till the residual image becomes indistinct. ? monoscope signal conditions: vsig = 6.0 4.0 or 6 2.0 (v) (shown in the right figure) v com = 5.7v input signal voltage (waveform applied to the measured pixels) 4.0v 0.5v 6.0v 0v optical transmittance output waveform 100% 90% 10% 0% ton t1 ton toff t2 toff ? r, g, b input signal condition for gray raster mode is given by vsig = 6.0 v 50 (v) where: v 50 is the signal amplitude which gives 50% of transmittance in v-t characteristics. black level white level vsig waveform 6.0v 0v 4.0v 2.0v 4.0v 2.0v ac component dc component
15 LCX032ANB example of back light spectrum (reference) 0.4 0.3 0.2 0.1 0 400 500 600 700 wavelength 380 780 [nm]
16 LCX032ANB description of operation 1. color coding color filters are coded in a delta arrangement. the shaded area is used for the dark border around the display. b r g b r g b r g b r g b r g b r g r b g r b g r b g r b g r b g r b r g b r g b r g b r g b r g b r g r b g r b g r b g r b g r b g r b r g b r g b r g b r g b r g b r g r b g r b g r b g r b g r b g r b r g b r g b r g b r g b r g b r g r b g r b g r b g r b g r b g r b r g b r g b r g b r g b r g b r r b g r b g r b g r b g r b g r g gate sw gate sw gate sw gate sw 537 3 521 13 2 2 218 222 gate sw gate sw green is not connected for only final stage. photo-shielding g b g b g b g b g b active area
17 LCX032ANB 2. lcd panel operations through current of the level shifter during power supply cutoff can be reduced by stb pin. (power save mode) power save mode is set at stb = low level. a vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 218 gate lines sequentially in every horizontal scanning period. a vertical shift register scans the gate lines from the top to bottom of the panel at dwn = high level. the selected pulse is delivered when the enable pin turns to high level. pal mode images are displayed by controlling the enable and vck pin. the enable pin should be high when not in use. a horizontal driver, which consists of horizontal shift registers, gates and cmos sample-and-hold circuits applies selected pulses to every 521 signal electrodes sequentially in a single horizontal scanning period. vertical and horizontal drivers address one pixel and then turn on thin film transistors (tfts; two tfts) to apply a video signal to the dot. the same procedures lead to the entire 218 521 dots to display a picture in a single vertical scanning period. pixel dots are arranged in a delta pattern, where sets of rgb pixels are positioned with 1.5-dot shifted against adjacent horizontal line. 1.5-dot shift of a horizontal driver output pulse against horizontal synchronized signal is required to apply a video signal to each dot properly. 1h reversed displaying mode is required to apply video signal to the panel. the video signal shall be input with polarity-inverted system in every horizontal cycle. timing diagrams of the vertical and the horizontal right-direction scanning (rgt = high level) display cycle are shown below:
18 LCX032ANB vertical display cycle 218h (13.84ms) 12 218 217 (1) vertical display cycle vd vst vck horizontal display cycle (47.3s) 123 45 175 174 (2) horizontal display cycle (right scan) hd hst hck1 hck2 ? hst is sampled at first for hck1. the horizontal display cycle consists of 521/3 = 174 clock pulses because of rgb simultaneous sampling. ? refer to description of operation "3. rgb simultaneous sampling." ? vst is sampled at first for vck. this lcd panel provides the following functions. right/left inverse mode up/down inverse mode these modes are controlled by two signals, rgt and dwn. rgt mode right scan left scan h l dwn mode down scan up scan h l
19 LCX032ANB 3. rgb simultaneous sampling horizontal driver samples r, g and b signal simultaneously, which requires the phase matching between r, g and b signals to prevent horizontal resolution from deteriorating. thus phase matching between each signal is required using an external signal delaying circuit before applying video signal to the lcd panel. two methods are applied for the delaying procedure: sample and hold and delay circuit. these two block diagrams are as follows. the LCX032ANB has the right/left inverse function. the following phase relationship diagram indicates the phase setting for the right scan (rgt = high level). for the left scan (rgt = low level), the phase setting shall be inverted between b and g signals. (1) sample and hold (right scan) (right scan) s/h s/h ac amp s/h ac amp s/h ac amp s/h (2) delay circuit (right scan) delay delay ac amp delay ac amp ac amp 4 3 b r g blue red green ckb ckr ckg ckg ckg hckn ckb ckr ckg blue red green b r g LCX032ANB LCX032ANB 2 4 3 2
20 LCX032ANB example of color filter spectrum (reference) 400 500 600 700 wavelength [nm] transmittance [%] 0 20 40 60 80 100 b g r color filter spectrum
21 LCX032ANB color display system block diagram an example of single-chip display system is shown below. y/color difference y/c lcd panel ntsc/pal LCX032ANB red green blue hck1 hst vst hck2 vck en stb +12v +3v vcom cxa3503r +12v dwn rgt blk control circuit (microcomputer, etc.) serial control
22 LCX032ANB notes on handling (1) static charge prevention be sure to take following protective measures. tft-lcd panels are easily damaged by static charge. a) use non-chargeable gloves, or simply use bare hands. b) use an earth-band when handling. c) do not touch any electrodes of a panel. d) wear non-chargeable clothes and conductive shoes. e) install conductive mat on the working floor and working table. f) keep panels away from any charged materials. g) use ionized air to discharge the panels. (2) protection from dust and dirt a) operate in clean environment. b) when delivered, a surface of a panel (polarizer) is covered by a protective sheet. peel off the protective sheet carefully not to damage the panel. c) do not touch the surface of a panel. the surface is easily scratched. when cleaning, use a clean-room wiper with isopropyl alcohol. be careful not to leave stain on the surface. d) use ionized air to blow off dust at a panel. (3) other handling precautions a) do not twist or bend the flexible pc board especially at the connecting region because the board is easily deformed. b) do not drop a panel. c) do not twist or bend a panel or a panel frame. d) keep a panel away from heat source. e) do not dampen a panel with water or other solvents. f) avoid to store or to use a panel in a high temperature or in a high humidity, which may result in panel damages.
23 LCX032ANB package outline unit: mm mass description molding material outside frame reinforcing board reinforcing material polarizing film f p c no 1 2 3 4 5 6 0.9g 16.0 0.15 8.0 0.25 (8.97) (6.63) 6.1 0.25 15.4 0.15 56.1 0.9 1.2 0.3 12.5 0.3 8.5 0.05 4 1 5 3 6 6 4-r1.0 active area 0.3 0.05 thickness of the connector incident light pin 1 pin 16 0.5 0.1 0.5 0.15 3.0 0.3 4.0 0.5 0.35 +0.04 -0.03 electrode(enlarged) 2 (40.7) 2.7 0.15 (0.4) (1.9) p 0.5 0.02 15 = 7.5 0.03 sony corporation

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